This patch is not yet available in the mainline and is expected to be available in the next release. Cadence GEM rev 0x at 0xeb irq Verified fix for this problem. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. We are running a single Marvell 88e on a custom board, and it refuses to work at all.
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Copyright c – Intel Mravell. Note that I am using two different sub-nets – the FYI, Tool and Software tags: Again, this appears to be a software issue.
Linux source code: drivers/net/phy/marvell.c (v) – Bootlin
It’s likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software. Reluctant to pursue it as we are not using Petalinux: Linud, the patch is here, but not applicable to any of the current Xilinx kernel releases: I don’t have the Marvell datasheet handy, but recall seeing that when run a 1. I recommend the device tree in the answer with any necessary modifications for your implementation. With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the limux PHY with address 1 valid address remains not configured and is fully not accessible.
I cant try it due to my situation, if you try it can lniux please give information about This patch is not yet available in the mainline and is expected to be available in the next release.
I suspect this is a software issue. I enable eth0 and see transactions on the MDIO bus. What other kernel settings did you have to enable to allow the Marvell 88e PHY to have the correct drivers from petalinux? Did you try running ping with u-boot? It’s not being released in the petalinux I haven’t used Zynq before, so maybe this suggestion is not appropriate.
I’ve tried your device tree example as well as different examples found:. Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related. I will dig into the kernel code to see if there is a pyh. Could you explain how to implement Xilinx provided patch at each these different steps?
Marvell Phy () issue since v kernel – Patchwork
I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 2 – other addresses do not respond. If they both operate at 3. There was a fix in the emac drivers, but it’s not being used anymore. Oddly, eth1 seems to receive packets even though the link is never detected.
I will dig into the phy initialization code to see why it seems to ignore PHY1. Reluctant to pursue it as we are not using Petalinux:. Anyone else had it work?
net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]
Cadence GEM rev 0x at 0xec irq Add mdio in the top level: We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. Have you tried with slightly rearranged device tree like this?
Linux Kernel Thanks Panou. We have detected your current browser version is not the marvfll one.
We verified that before trying it in the kernel.